As a Static Timing Analysis (STA) Engineer you will handle pre-layout and post-layout timing for state-of-the-art digital ICs/SoCs & FPGAs on the most critical programs across the  Defense and Security enterprise. You will collaborate with other electronics groups across the company and around the world from the early design stages until signoff to help achieve first pass success. You will be working with a large physical design team within the company and outside of the company for timing convergence. STA engineers are required work with IP team, EDA vendors, and Foundry for the design closure.
Position Responsibilities

• Responsible for STA analysis and convergence throughout the ASIC cycle
• Responsible for finding solution for intricate timing paths (Digital, analog and mixed signal)
• Facilitate STA methodology in collaboration with other STA leaders
• Generate timing constraints for multiple ASICs and FPGAs
• Generate tool independent timing constraints that will work for synthesis, place & route and static timing analysis
• Responsible for intricate cross domain timing path closure
• Extract timing information from circuit analysis and develop primary input setup/hold timing constraints as well as primary output required arrival time (RAT) and skew timing constraints
• Programming skills with Python, TCL, Perl, Unix shell etc.
• Help train new engineers

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