As a member of the Graphics team, the successful applicant will help develop new flows/methodologies and algorithms to improve power, performance and area (PPA) on state-of-the-art GPU cores while working closely with the graphics microarchitecture design and implementation teams. The successful candidate will possess basic understanding of RTL design and ASIC design flow from RTL to GDS such as synthesis, static timing analysis, formal verification, physical design, ECO generation and verification. They will collaborate with multiple functional teams including design, technology, power, implementation, sign-off and post-silicon to drive PPA improvements into GPU cores.

Knowledge and experience in the following is a definite advantage:ooo
• Implementation and delivery of GPU cores from RTL to GDSII
• Semi-custom design flow and methodology development
• Identifying areas for flow and process improvements
• Verilog and System-Verilog languages
• RTL synthesis using physically aware tools
• Design constraint management for power, timing, clocking, interfaces
• Formal Verification for RTL-netlist and netlist-netlist checks
• Clock Tree Analysis and Optimization
• ECO methods for functional and timing fixes
• Managing design goals and tradeoffs in power, performance, and area

Preferred Qualifications
At-least 5-7 years of experience developing methodologies for PPA improvement
Basic understanding of digital design and RTL development
Hands on experience with EDA tools such as Synopsys Fusion Compiler, Synopsys RTL-Architect, PrimePower,PrimeTime and Prime Closure
Script writing experience in UNIX shell, Python, Perl and/or TCL
Excellent interpersonal and analytical skills as well as ability to work independently
Highly motivated, excellent team spirit, obsession with deliverable quality and customer oriented

Education Requirements Preferred: Master’s, Computer Engineering and/or Computer Science and/or Electrical Engineering
Required: Bachelor’s, Computer Engineering and/or Computer Science and/or Electrical Engineering

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