Senior Staff Embedded Software Engineer – AI Accelerator

Engineer

Senior Staff Embedded Software Engineer – AI Accelerator

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  • Date posted
    August 10, 2026
  • Expiration date
    November 10, 2026
  • Application ends
    November 10, 2026

Our Data Center AI Software team is leading the development of low-level firmware and platform software for next-generation data center and cloud-scale AI/compute systems.
This is a technical leadership role spanning SoC bring-up, platform architecture, performance optimization, reliability engineering, and deployment at hyperscale. You will drive cross-functional initiatives and set technical direction across firmware domains powering cloud inference and acceleration platforms.
You will collaborate closely with hardware, system software, infrastructure, and validation teams, as well as external partners, to deliver robust, scalable, and production-ready firmware solutions.
Key Responsibilities

Lead architecture, design, and development of firmware and low-level system software across SoC, board, and platform levels

Own end-to-end firmware strategy across boot, reset, debug, security, power, RAS, IPC, and platform services

Drive SoC and platform bring-up at scale, including system integration and validation across multiple product generations

Provide technical leadership and mentorship to engineers; set coding, design, and quality standards

Define and influence firmware architecture for scalability, reliability, and performance in large-scale cloud deployments

Lead cross-functional design reviews, system debugging, and root-cause analysis for complex platform issues

Establish best-in-class debuggability, observability, and CI/CD practices, including automation and pre-silicon/post-silicon validation strategies

Drive customer and production issue resolution, including deep field debugging and long-term corrective actions

Collaborate with ODMs, silicon vendors, and manufacturing partners to ensure successful platform deployment and ramp

Influence roadmap and long-term technical direction for firmware and platform software in AI accelerator systems

Drive continuous improvement across firmware teams, identifying systemic process-level improvements and scaling best practices
Required Qualifications

Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, Computer Science, or related field

12+ years of experience in firmware or low-level system software development, with demonstrated technical leadership

Expert-level proficiency in C/C++, with strong scripting skills (Python, Bash)

Deep experience in SoC bring-up, hardware/software integration, and system-level debugging

Strong understanding of computer architecture, including memory hierarchy, interrupts, DMA, coherency, and interconnects

Proven ability to lead complex debugging efforts using JTAG, trace, logs, and instrumentation

Extensive experience working in Linux-based environments and RTOS such as Zephyr
Preferred Qualifications

Prior experience architecting firmware for cloud or hyperscale data-center platforms

Strong familiarity with platform management ecosystems

Deep expertise in one or more areas:

Boot architecture, secure boot, and firmware security

Power management, thermal control, and RAS at scale

Performance optimization and system stress validation

Firmware CI/CD pipelines, simulation, and automation frameworks

Experience with AI accelerators, heterogeneous compute systems, or high-speed interconnects (PCIe, CXL, NVLink, ESUN, UAL, etc.)

Proven track record of working with hardware vendors, ODMs, and manufacturing ecosystems

Demonstrated ability to influence architecture and roadmap across organizations
Leadership Expectations (Senior Staff Level)

Act as a technical authority and decision maker across firmware domains

Drive alignment across teams and organizations to deliver cohesive platform solutions

Mentor senior engineers and grow technical talent within the organization

Balance hands-on engineering with strategic impact, contributing both at code level and architecture level

Anticipate and mitigate system-level risks across product lifecycles

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