We are looking for a highly skilled Physical Design Engineer to join our team . You will play a critical role in the physical implementation of subchips, ensuring performance, power, and area (PPA) goals are met through rigorous design cycles.

Key Responsibilities :

– End-to-End Implementation : Independently handle physical design activities at the subchip level.

– Timing Closure : Perform detailed Static Timing Analysis (STA) and drive timing closure to meet project milestones.

– Physical Verification : Own DRC/LVS closure for assigned subchips, ensuring clean, high-quality deliverables.

– Collaboration : Work closely with integration and signoff teams to resolve complex physical and timing issues.

– Ownership : Take complete ownership of assigned blocks, from initial floorplan to final GDSII delivery.

Required Skills & Experience :

Experience : 4+ years of hands-on experience in Physical Design (P&R).

Tools Proficiency :

1. Place & Route : Expert-level knowledge of Cadence Innovus.

2. STA : In-depth experience with Synopsys PrimeTime.

Core Competencies :

i. Strong understanding of subchip-level timing closure.

ii. Proven track record in Physical Verification (PV) and DRC closure.

iii. Familiarity with modern CMOS process nodes and low-power design techniques.

Soft Skills :

– Strong analytical mindset, excellent communication, and the ability to work collaboratively in a fast-paced environment.

Are you interested in this position?

Apply by clicking on the “Apply Now” button below!

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